A semiconductor device such as a flash memory device has a non-volatile characteristic in which stored data may be held although the power supply is stopped. The flash memory device can electrically write or erase data. The flash memory device may store data using a difference in a threshold voltage of cells of transistor type according to existence of charges in floating gates isolated electrically. Meaning, data having a logic level “0” and a logic level “1” may be stored by storing charges in the floating gates or discharging charges from the floating gates.
In order to achieve high integration, unit patterns configuring the flash memory device may be changed in various configuration, in order to reduce a unit cell area. For example, gate patterns, which may be used as word lines of the flash memory device, may include bent portions in order to form contact plugs adjacent thereto.
As illustrated in example FIG. 1, a flash memory device can include plurality of cell gate patterns 10 arranged in parallel on and/or over a semiconductor substrate. Each cell gate pattern 10 may include a first portion extending in a straight-line and a bent second portion. Cell gate patterns 10 having the first and second portions may be symmetrically arranged in a single direction. Accordingly, the first portions of a pair of adjacent cell gate patterns 10 may be separated from each other with first distance d1 and the second portions of the pair of adjacent cell gate patterns 10 may be separated from each other with second distance d2. Second distance d2 may be lesser than first distance d1. Since the second portions of the pair of cell gate patterns 10 may be formed with second distance d2, the second portion of another cell gate pattern 10 adjacent to the second portions of the pair of cell gate patterns 10 may be separated from each other with third distance d3 that is greater than second distance d2.
Spacers 12 may be formed on both sidewalls of cell gate patterns 10. A plurality of first contact plugs 14a may be arranged separate from each other between the first portions which are separated from each other with first distance d1, and second contact plugs 14b may be provided at both sides of the second portions. First contact plugs 14a and second contact plugs 14b may penetrate through an oxide film for covering cell gate patterns 10 and spacers 12 to contact the semiconductor substrate.
Second distance d2 between the second portions may be very small as denoted by portion A. In addition, spacer 12 may be present between the second portions in portion A. Accordingly, an aspect ratio of a gap which is present in portion A may significantly increase. As a result, the oxide film for covering cell gate patterns 10 and spacers 12 may not fill the gap which is present in portion A, thereby forming a void. Accordingly, a conductive material for forming first contact plugs 14a and second contact plugs 14b may be filled in the gap of portion A. Thus, an electrical bridge phenomenon occurs to cause failure of the flash memory device.